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1、题目
2、分析
a为0时，q为1，当a变为1时，q在下一个时钟周期变为0
3、代码
module top_module ( input clk, input a, output q ); always @(posedge clk) begin q <= (~ a); end endmodule4、结果
verilog HDLBits刷题[Bulid a circuit from a simulation waveform]“Sim/circuit7”---Sequential circuit7