一、pointer reference input可以约束为axis;void array_FIFO (dout_t d_o[4], din_t *d_i, didx_t idx[4]) {#pragma HLS INTERFACE axis register both portd_iint i;// Breaks FIFO interface d_o[3] d_i[2];For_Loop: for (i0;i4;i) {d_o[i] d_i[idx[i]];//d_o[i] d_i[i];//printf(idx[i]%d\n\r,idx[i]);}}仿真情况// RTL Simulation : 0 / 3 [0.00%] 110000// RTL Simulation : 0 / 3 [200000000.00%] 40000118000// RTL Simulation : 0 / 3 [400000020.00%] 80000122000// RTL Simulation : 0 / 3 [600000040.00%] 120000126000// RTL Simulation : 0 / 3 [800000060.00%] 160000130000可以看到仿真挂死了一直在running但是始终没有完成仿真为什么因为你将指针约束为axis接口的时候一定要指定depth的深度如果没有指定depth深度那就是有问题的。将上述代码修改为void array_FIFO (dout_t d_o[4], din_t *d_i, didx_t idx[4]) {#pragma HLS INTERFACE axis register both depth4 portd_iint i;// Breaks FIFO interface d_o[3] d_i[2];For_Loop: for (i0;i4;i) {d_o[i] d_i[idx[i]];//d_o[i] d_i[i];//printf(idx[i]%d\n\r,idx[i]);}}可以看到将axis加入了depth指定后仿真ok了。可以约束为s_axilite;void array_FIFO (dout_t d_o[4], din_t *d_i, didx_t idx[4]) {#pragma HLS INTERFACE s_axilite register portd_iint i;// Breaks FIFO interface d_o[3] d_i[2];For_Loop: for (i0;i4;i) {d_o[i] d_i[idx[i]];//d_o[i] d_i[i];//printf(idx[i]%d\n\r,idx[i]);}}上述代码综合会报错ERROR: [SYNCHK 200-61] array_FIFO.c:102: unsupported memory access on variable d_i which is (or contains) an array with unknown size at compile time.INFO: [SYNCHK 200-10] 1 error(s), 0 warning(s).ERROR: [HLS 200-70] Synthesizability check failed.command ap_source returned error codewhile executing修改代码void array_FIFO (dout_t d_o[4], din_t *d_i, didx_t idx[4]) {#pragma HLS INTERFACE s_axilite register depth 4 portd_iint i;// Breaks FIFO interface d_o[3] d_i[2];For_Loop: for (i0;i4;i) {d_o[i] d_i[idx[i]];//d_o[i] d_i[i];//printf(idx[i]%d\n\r,idx[i]);}}还是一样报错为什么因为#pragma HLS INTERFACE s_axilite register depth 4 portd_i只是说明寄存器的个数是4个综合工具还是不知道din_t *d_i指针到底要分配多大空间所以综合报错再次修改顶层函数代码为void array_FIFO (dout_t d_o[4], din_t *d_i, didx_t idx[4]) {//#pragma HLS INTERFACE s_axilite register portd_i#pragma HLS INTERFACE s_axilite register depth4 portd_iint i;// Breaks FIFO interface d_o[3] d_i[2];For_Loop: for (i0;i4;i) {//d_o[i] d_i[idx[i]];d_o[i] *d_i;}}测试激励为#include array_FIFO.hint main () {din_t d_i[4];dout_t d_o[4];didx_t idx[4];int i, retval0;FILE *fp;// Create input datafor (i0;i4;i) {d_i[i] i10;//idx[i] i;idx[i] 3-i;}// Call the function to operate on the dataarray_FIFO(d_o,d_i,idx);// Save the results to a filefpfopen(result.dat,w);fprintf(fp, Din Dout\n);for (i0;i4;i) {fprintf(fp, %d %d\n, d_i[i], d_o[i]);}fclose(fp);// Compare the results file with the golden resultsretval system(diff --brief -w result.dat result.golden.dat);// if (retval ! 0) {// printf(Test failed !!!\n);// retval1;// } else {// printf(Test passed !\n);// }// Return 0 if the test passes//return retval;return 0;}rtl仿真的结果可以约束为m_axi-----------用于访问DDR可以约束为ap_none可以约束为ap_stable可以约束为ap_ack可以约束为ap_vld可以约束为ap_hs可以约束为ap_fifo可以约束为ap_bus二、pointer reference output可以约束为axis;可以约束为s_axilite;可以约束为m_axi可以约束为ap_none可以约束为ap_ack可以约束为ap_vld可以约束为ap_hs可以约束为ap_fifo可以约束为ap_bus三、pointer reference input_output可以约束为axis;可以约束为s_axilite;可以约束为m_axi可以约束为ap_none可以约束为ap_ack可以约束为ap_vld可以约束为ap_hs可以约束为ap_bus
